Logic Minimization Algorithms for VLSI Synthesis (Record no. 824974)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00461nam a22001817a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780898381641 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.38173 BRA |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Brayton Robert K |
| 245 ## - TITLE STATEMENT | |
| Title | Logic Minimization Algorithms for VLSI Synthesis |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1 |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Boston |
| Name of publisher, distributor, etc | KLuwer Academic Publishers |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 193 |
| 440 ## - SERIES STATEMENT/ADDED ENTRY--TITLE | |
| Series Title | Logic Minimization Algorithms for VLSI Synthesis |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VLSI |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Hachtel Gary D |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Cost, replacement price | Bill Date | Koha item type | Bill Number |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Not For Loan | Reference | GRIET Library and Information Centre | GRIET Library and Information Centre | Reference | 29/05/2018 | BSP Books | 12636.00 | 621.38173 BRA | 118886 | 29/05/2018 | 12636.00 | 31/03/2018 | Books | 1287 |