Chip Design for Submicron VLSI CMOS Layout Simulation
Material type: TextSeries: Chip Design for Submicron VLSI CMOS Layout SimulationPublication details: New Delhi Cengage Learning 2017Edition: 1Description: 411ISBN: 9788131501955Subject(s): VLSIDDC classification: 621.3815 UYEItem type | Current library | Collection | Call number | Status | Date due | Barcode |
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Books | GRIET Library and Information Centre Reference | Reference | 621.3815 UYE (Browse shelf(Opens below)) | Not For Loan | 123627 |
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