000 00436nam a22001697a 4500
003 OSt
020 _a9788131501955
082 _a621.3815 UYE
100 _aUyemura John P
245 _aChip Design for Submicron VLSI CMOS Layout Simulation
250 _a1
260 _aNew Delhi
_bCengage Learning
_c2017
300 _a411
440 _aChip Design for Submicron VLSI CMOS Layout Simulation
650 _aVLSI
942 _2ddc
_cBK
999 _c825709
_d825709