Chip Design for Submicron VLSI CMOS Layout Simulation
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TextSeries: Chip Design for Submicron VLSI CMOS Layout SimulationPublication details: New Delhi Cengage Learning 2017Edition: 1Description: 411ISBN: 9788131501955Subject(s): VLSIDDC classification: 621.3815 UYE
| Item type | Current library | Collection | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|---|
| Books | GRIET Library and Information Centre Reference | Reference | 621.3815 UYE (Browse shelf(Opens below)) | Not For Loan | 123627 |
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| 621.3815 SHA Design of Electronic Circuits and Computer Aided Design | 621.3815 SHA Design of Electronic Circuits and Computer Aided Design | 621.3815 TOO Practical Digital Electronics Handbook | 621.3815 UYE Chip Design for Submicron VLSI CMOS Layout Simulation | 621.38152 BOS Semiconductor Materials and Devices Science and Technology | 621.38152 SHA Semiconductor Electronics | 621.38152 STR Solid State Electronic Devices |
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